Elecrow PCB Gerber Review Checklist Before Fabrication

Submitting Gerber files is the last gate before PCB fabrication begins. Once copper is etched and drill hits are made, design mistakes become expensive rework, schedule delays, or scrapped panels. A structured Gerber review catches unit errors, missing layers, ambiguous fab notes, and assembly conflicts while changes are still free. This Elecrow PCB Gerber review checklist gives engineering teams a practical sequence to validate fabrication data before an order is placed.

Gerber is not a single file. It is a coordinated set of copper, mask, silk, drill, and outline data that must agree with the stackup, impedance plan, and assembly requirements. Many fabrication holds trace back to issues that a ten-minute visual check would have found: mirrored layers, wrong decimal format, or a drill file that does not match the board thickness. Treat Gerber review as part of design release, not an optional step after the quote is submitted.

Confirm you are releasing the correct revision

Start with revision control. The Gerber package must match the schematic revision, BOM, placement data, and assembly drawing released for the same build. File names should include a revision identifier or be archived in a folder that cannot be confused with an older export. Compare the board title block, date code field, or internal part number embedded in silk against your release record.

If the design changed after the last quote, regenerate all layers from the CAD tool rather than editing individual Gerber files by hand. Partial updates are a common source of mismatched drill counts, stale copper pours, or outline dimensions that no longer match the routed board. When working with Elecrow, submit one coherent package per order so DFM review applies to the exact data the fabricator will use.

Verify layer completeness

A standard multilayer PCB release typically includes top and bottom copper, inner layers, top and bottom solder mask, top and bottom silkscreen, board outline, drill data, and optional paste layers. Missing inner layers or a forgotten bottom mask will stop production or force assumptions that may not match your intent.

• Top copper and bottom copper are present and named consistently.
• All inner signal and plane layers are included for the ordered layer count.
• Top and bottom solder mask files exist unless the build is a defined prototype exception.
• Silkscreen layers are present on both sides if components or markings appear on both sides.
• Board outline or profile layer defines the finished board shape without ambiguity.
• Drill file or embedded drill data covers every plated and non-plated hole.
• Paste layers are included when the fabricator or assembly house uses them for stencil generation.

For a deeper explanation of what each file represents, review the what are Gerber files guide on the Elecrow blog.

Check units, format, and polarity

Gerber data can be exported in metric or imperial units, with 2:4, 2:5, or 2:6 decimal formats depending on the CAD tool and fabricator preference. A mismatch between the drill file units and the copper layer units produces holes that are ten times too large or too small. Open the release in a Gerber viewer and confirm that dimensions match the intended board size in millimeters or inches.

Verify polarity on every layer. Copper layers should show pads and traces as positive features unless your supplier explicitly expects negative polarity for certain plane layers. Solder mask is often exported as negative data where openings define exposed copper; confirm that pads are exposed and traces are covered as intended. A reversed mask layer will leave the entire board masked except where traces should be covered, which is a classic fabrication stop.

Use a reliable viewer before submission

Load all layers together with the correct stack order. Toggle layers on and off to confirm alignment. Pads on top copper should align with mask openings, drill hits, and paste apertures. Inner layers should register with through-hole locations. Misregistration in the viewer often indicates a wrong offset, missing mirror, or an outline that was scaled incorrectly during export.

Zoom into fine-pitch areas, castellated edges, and impedance-critical traces. Look for slivers, acute-angle copper, and mask slivers between closely spaced pads. These may pass electrical DRC in CAD but fail DFM at the fabricator.

Review drill data and mechanical features

Drill files must list every tool size, distinguish plated from non-plated holes, and agree with the physical stackup. Compare the drill chart against the board thickness and via sizes used in the layout. Aspect ratio violations and minimum hole size issues are frequent causes of fab holds.

Confirm that mounting holes, slots, and cutouts appear on the correct mechanical layers with clear plating instructions. Non-plated holes should not be treated as vias. Castellated holes, edge plating requests, and counterbores need explicit notes in the fab drawing or README, not only implicit geometry in the Gerber.

Via-in-pad locations deserve special attention. If thermal pads under QFN or power devices use vias, state whether those vias must be filled, plugged, or capped. Open vias in SMT pads create assembly yield problems that fabrication alone cannot fix. Align drill requirements with the Elecrow PCB drill and via design guidance before release.

Validate solder mask and surface finish intent

Mask openings define where copper is exposed for soldering and testing. Check that BGA pads, fine-pitch ICs, test points, and edge connectors are fully opened with adequate mask clearance. Solder mask defined pads versus copper defined pads change fabrication tolerance; note your preference in fab instructions if the design relies on mask registration for fine pitch.

Specify solder mask color, surface finish, and any controlled impedance requirements in the order notes. HASL, ENIG, immersion silver, and OSP each affect SMT yield and shelf life differently. If the board will proceed to PCBA at Elecrow, choose a finish compatible with your component package mix and storage plan. The Elecrow PCB solder mask selection article explains trade-offs that belong in the same review pass as the Gerber files.

Silkscreen clarity and assembly marks

Silkscreen should identify polarity, pin one, connector labels, and version strings without covering pads. Reflow solder cannot wet through silkscreen on a pad. Check that designators remain readable after assembly where they support inspection and rework.

Include a fabrication drawing or stackup table when the design uses controlled impedance, specific dielectric materials, or nonstandard core thickness. Gerber alone does not communicate impedance targets; the fab note and stackup document do.

Run DFM checks aligned with your process

Design for manufacturability rules differ by fabricator capability and by whether the board is prototype or production. Before submission, run CAD DFM and a Gerber-level review against known supplier limits for trace width, spacing, annular ring, copper balance, and drill-to-copper clearance.

• Minimum trace and space meets the ordered process class, not only the tool default.
• Annular rings on vias and through-hole pads meet IPC class targets where reliability requires it.
• Copper pour spokes and thermal reliefs are intentional, not accidental slivers.
• Board outline includes correct corner radius, slot dimensions, and panelization breakaway if supplied.
• Fiducials and tooling holes are present if the assembly house requires them on the fab panel.
• Copper balance across layers is reasonable to reduce bow and twist risk on multilayer boards.

Many issues are easier to fix in layout than after CAM engineering at the supplier. The PCB design for manufacturing article provides broader DFM context that complements this Gerber-specific checklist.

Prepare the submission package

Organize files so the fabricator does not guess layer functions. Use clear filenames or a standard archive structure. Include a readme with board thickness, layer count, surface finish, mask color, impedance requirements, material specification if non-default, and contact information for engineering questions.

If panelization is handled by the customer, include breakaway method, mouse bite or V-score preference, and keep-out zones around the array. If the supplier will panelize, provide a single-up outline and state quantity per panel constraints if known. Mixed approaches between quote and file release cause unnecessary email cycles.

Cross-check against assembly inputs

Fabrication data must align with PCBA inputs when the same board continues to assembly. Board thickness, finish, mask color, and copper weight affect stencil design and reflow behavior. Confirm that the outline matches the assembly drawing and that tooling holes do not conflict with component keep-outs on the finished panel.

When ordering turnkey PCB fabrication and assembly, one consistent revision across Gerber, BOM, and centroid data prevents mismatched builds. Submit through the Elecrow shop with linked files or contact Elecrow support when the design needs engineering review before production.

Final release checklist

Walk through this summary immediately before upload. Assign a second reviewer when possible; fresh eyes catch mirrored layers and unit errors that the layout engineer has stopped seeing.

• Revision matches schematic, BOM, and assembly release for this build.
• All required copper, mask, silk, outline, and drill layers are present and correctly polarized.
• Units and decimal format are consistent across copper and drill data.
• Gerber viewer inspection shows aligned pads, holes, mask openings, and outline.
• Fab notes specify thickness, layer count, finish, mask color, impedance, and via-in-pad treatment.
• DFM limits for trace, space, annular ring, and drill sizes are verified against supplier capability.
• Mechanical features, slots, and NPTH holes are documented with plating rules.
• Submission package is organized with a readme or fab drawing for non-Gerber requirements.

A disciplined Gerber review takes less time than a fabrication hold, a remake, or an assembly debug cycle caused by a missing layer or wrong drill unit. Make it a standard gate in every Elecrow PCB release, from first prototype through production. For more fabrication and assembly guidance, browse the Elecrow blog before your next order.