A PCB stackup is an electrical, mechanical, and manufacturing decision made before routing starts. It defines how copper, dielectric, planes, impedance, return currents, and heat are arranged through the board thickness. For reliable Elecrow PCBA, stackup planning should not be treated as a final documentation task. It should guide component placement, layer assignment, routing rules, and the fabrication quote from the first schematic review.
A good stackup makes a design easier to manufacture and easier to debug. It provides predictable impedance for high-speed signals, low-inductance power distribution, controlled electromagnetic emissions, and enough mechanical strength for assembly. A poor stackup can force last-minute trace-width changes, cause marginal interfaces, increase warpage during reflow, or make a four-layer board behave like a noisy two-layer board.
Define the electrical and assembly requirements first
Start with the product rather than the layer count. List interfaces, edge rates, clock frequencies, power rails, analog sensitivity, RF sections, connector locations, enclosure limits, and expected operating environment. Fast edges usually matter more than nominal clock rate. A modest-frequency clock with sub-nanosecond transitions can require controlled impedance and a continuous return path, while a slow control bus may not.
Also document PCBA constraints. Large BGAs may need additional routing layers or microvias. Fine-pitch QFNs need a solid reference plane and carefully managed escape routing. Heavy connectors, heat sinks, and panel mounting points may require a thicker finished board. Surface-mount assembly places thermal stress on the stackup, so material symmetry and copper balance affect yield as well as electrical behavior.
Choose a realistic layer count
Two layers can work for low-speed, low-density designs when one layer remains substantially solid ground. However, routing power and signals across both sides often fragments the return path. For many mixed-signal products, four layers are a practical minimum: top signal, ground plane, power plane or mixed routing layer, and bottom signal. This gives critical traces nearby reference planes and reduces loop area.
Six and more layers are justified by density, high-speed routing, multiple power domains, RF isolation, or the need to route between BGA pads without compromising planes. Do not add layers only to make routing convenient; assign a job to each layer. A layer with no clear purpose increases cost without necessarily improving performance.
- Signal layers: Carry controlled-impedance routes, local fanout, and low-speed connections with known reference planes.
- Ground planes: Provide continuous return-current paths, shielding, and a low-impedance reference for signals and power.
- Power planes: Distribute stable rails while working with adjacent ground planes to form useful plane capacitance.
- Mixed layers: Require discipline; preserve plane continuity under critical routes and avoid creating narrow return bottlenecks.
Place reference planes close to signal layers
Controlled impedance comes from trace geometry and the dielectric material around it. The distance from a trace to its reference plane strongly affects impedance, field containment, crosstalk, and radiation. A top-layer microstrip located close to Layer 2 ground can use a practical trace width, while the same trace over a distant plane may need an extremely wide or narrow geometry that is harder to fabricate consistently.
For high-speed signals, each routing layer should have an adjacent solid plane. A common four-layer arrangement is Signal/Ground/Power/Signal, but its suitability depends on dielectric spacing. If the bottom signal layer is far from the power plane, its impedance may be harder to control. Discuss the proposed construction with Elecrow before locking trace widths. The fabricatorâs actual prepreg thickness, copper weight, and dielectric constantânot a generic calculatorâshould drive the final impedance rules.
Protect the return path
High-frequency return current follows the path of lowest inductance, usually directly beneath a trace on its reference plane. A split, void, slot, or unrelated plane crossing forces that current to detour, increasing loop area and noise. Keep high-speed and sensitive analog signals over uninterrupted ground. When a signal changes layers, place a nearby ground stitching via so the return current can transition with it.
A power plane can be an acceptable reference for some signals, but it is less robust than ground because its voltage may vary with load and its boundaries can be fragmented. Do not route a differential pair over a split merely because the two traces remain together; both traces still need a continuous electromagnetic reference.
Specify impedance as a requirement, not a guess
Interfaces such as USB, Ethernet, HDMI, PCIe, DDR, LVDS, CAN FD, and RF feeds often require specific single-ended or differential impedance. State the target impedance, tolerance, layer, copper weight, and whether the value is measured single-ended or differentially. Add a controlled-impedance table to the fabrication notes and identify the applicable nets in the CAD constraints.
A common error is copying a trace width from an old project. Even if both boards use âFR-4,â differences in resin content, copper thickness after plating, dielectric height, and solder mask can change impedance. Ask Elecrow for an impedance coupon or fabrication confirmation when an interface has a tight budget. Then update the PCB rules to match the approved construction rather than forcing the manufacturer to infer intent.
- Define target impedance and allowable tolerance for each critical net class.
- Use the fabricator-provided stackup to calculate widths, spacing, and differential-pair geometry.
- Keep paired traces on the same layer and avoid unnecessary layer transitions.
- Match length only where the protocol timing budget requires it; avoid decorative length tuning.
- Document test-coupon requirements for demanding designs.
Balance copper for fabrication and reflow
Copper distribution affects etching, lamination, drilling, plating, and thermal behavior during SMT reflow. A board with a large copper pour on one outer layer and sparse copper on the opposite side can bow or twist as it heats. That warpage can reduce solder-joint reliability, especially under BGAs and large bottom-terminated components. Aim for reasonably balanced copper coverage across opposing layers and avoid abrupt transitions between solid copper and empty areas.
Balance does not mean duplicating every power shape on the opposite layer. Electrical integrity comes first. Use nonfunctional copper, thieving, or plane planning only after verifying that the added copper does not create antenna structures, capacitively couple into sensitive circuits, or complicate isolation requirements. Keep pour clearances consistent and ensure thermal-relief settings work for both solderability and current capacity.
Select copper weight with the whole process in mind
Heavier copper improves current handling and spreading resistance but changes manufacturable trace and space limits, impedance geometry, drill aspect ratio, and etching accuracy. External copper also receives plating, so finished thickness can be greater than the starting foil. For a high-current rail, consider a wider route, multiple vias, local copper pours, or a dedicated plane before selecting heavy copper throughout the board. This may be more economical and easier to assemble.
Plan vias, holes, and thermal paths
Vias are part of the stackup strategy. Through vias connect all layers but consume routing area and create stubs on high-speed paths. Blind, buried, and microvias enable dense routing but add manufacturing complexity and must be coordinated with the selected layer build. Do not specify via types based solely on CAD capability. Confirm the fabrication limits, annular ring, aspect ratio, and reliability requirements with Elecrow.
For thermal pads under power ICs, use an array of small vias to conduct heat into internal or back-side copper. Decide whether these vias are tented, plugged, filled, or left open. Open vias can wick solder away from a thermal pad; filled or capped solutions may be preferable for fine-pitch or high-reliability assemblies. The stencil design and reflow profile must support the same decision.
Separate noise sources without breaking ground
Mixed-signal layouts benefit from physical zoning rather than indiscriminate ground splits. Keep switching regulators, inductors, high-current loops, clocks, and digital connectors away from low-level analog inputs and RF sections. Use a continuous ground plane underneath both regions, then control where signals cross between them. Connect analog and digital domains according to the converter or system architecture, not according to an arbitrary single-point rule.
For RF, preserve the manufacturer-recommended keep-out areas, ground-via fences, feed geometry, antenna clearance, and dielectric assumptions. A stackup revision can change antenna tuning or RF feed impedance. Treat it as part of the RF design verification, not just a manufacturing substitution.
Release clear fabrication information
Include the proposed stackup, finished thickness, material requirements, copper weights, impedance notes, drill requirements, surface finish, and special via instructions in the fabrication package. Cross-check that Gerber or ODB++ layer names map clearly to the intended construction. The Elecrow PCBA manufacturing process is useful context for connecting board fabrication choices to assembly outcomes.
Before ordering through the Elecrow shop, review the stackup with the PCB supplier and confirm it remains compatible with component pitch, BGA escape, and reflow needs. For a complete prototype-to-build handoff, also use the turnkey PCB assembly guide and contact Elecrow support with any special constraints. A documented, fabrication-aware stackup removes uncertainty early and gives a PCBA team a stable platform for reliable routing, assembly, and test.